Field of the Invention
This invention relates generally to the field of computer processors and software. More particularly, the invention relates to a method and apparatus for implementing dynamic portbinding within a reservation station.
Description of the Related Art
In a processor capable of out-of-order execution, instruction dispatching is stalled when there is a conflict for a particular functional unit or when a dispatched instruction depends on the result of an instruction that is not yet computed. In order to prevent or mitigate stalls in decoding, a reservation station (RS) may be used between the decode and execute stages of the processor. The decode stage decodes instructions and places the resulting micro-operations (uops) into the reservation station. Uops are examined in the reservation station to identify those which can be dispatched to the functional units of the execution unit (i.e., those for which source operands and functional units are available). Data-ready uops are dispatched from the reservation station out of program order.
Uops may be dispatched from the reservation station via multiple dispatch ports. Existing processor architectures implement reservation stations 10s of buffer entries for uops and which typically support many read ports to read out uops at dispatch time each cycle. Given the high latency associated with memory operations, a larger reservation station buffer would be beneficial for performance (e.g., to dispatch uops while waiting on high latency loads). However, a larger reservation station with many read ports would severely impact timing.